PeRex: A Power Efficient FPGA-based Architecture for Regular Expression Matching

Regular expression is an important approach which is widely used in string pattern matching. And in many pragmatic applications string pattern matching is the most compute intensive task which takes majority processing time, therefore, in order to improve system efficiency many works have been done around hardware implementation of regular expression matching. However, the traditional design approaches pay more attention on the implementation methods as well as their efficiency than the power consumption. In this paper we provide a power efficient regular expression matching architecture (PeRex). By taking full use of both rising and trailing edges of the system clocks such architecture is able to match two characters in a single system cycle. So, by maintaining the high performance and throughput the architecture in this paper is able to work in a lower clock frequency, consequently it will decrease the dynamic power consumption remarkably. Analyzed by XPower, which offered by Xilinx Inc., our approach is able to save dynamic power consumption by1.7 times comparing to traditional approaches on Virtex-V XC5VLX30 FPGA device.