An optimizer for hardware synthesis
A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decompos...
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| Veröffentlicht in: | IEEE design & test of computers 1990-10, Vol.7 (5), p.20-36 |
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| container_end_page | 36 |
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| container_title | IEEE design & test of computers |
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| creator | Bhasker, J. Lee, H.-C. |
| description | A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.< > |
| doi_str_mv | 10.1109/54.60604 |
| format | Article |
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The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.< ></description><identifier>ISSN: 0740-7475</identifier><identifier>EISSN: 1558-1918</identifier><identifier>DOI: 10.1109/54.60604</identifier><identifier>CODEN: IDTCEC</identifier><language>eng</language><publisher>IEEE Computer Society</publisher><subject>Circuit simulation ; Circuit synthesis ; Control systems ; Costs ; Hardware ; Logic ; Network synthesis ; Parallel processing ; Program processors ; Testing</subject><ispartof>IEEE design & test of computers, 1990-10, Vol.7 (5), p.20-36</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c303t-be5364485b652a4660f7da50c4e3475f86a3ffbce628af84548b29639ec053943</citedby><cites>FETCH-LOGICAL-c303t-be5364485b652a4660f7da50c4e3475f86a3ffbce628af84548b29639ec053943</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/60604$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/60604$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bhasker, J.</creatorcontrib><creatorcontrib>Lee, H.-C.</creatorcontrib><title>An optimizer for hardware synthesis</title><title>IEEE design & test of computers</title><addtitle>MDT</addtitle><description>A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. 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Preliminary test results for the analyzer are presented.< ></description><subject>Circuit simulation</subject><subject>Circuit synthesis</subject><subject>Control systems</subject><subject>Costs</subject><subject>Hardware</subject><subject>Logic</subject><subject>Network synthesis</subject><subject>Parallel processing</subject><subject>Program processors</subject><subject>Testing</subject><issn>0740-7475</issn><issn>1558-1918</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1990</creationdate><recordtype>article</recordtype><recordid>eNo90EtLxDAUBeAgCtZRcOuuIIibjjfNezkMvmDAja5DmrlhKn2ZdJDx11utuDqL83EvHEIuKSwpBXMn-FKCBH5EMiqELqih-phkoDgUiitxSs5SegcASqXMyPWqy_thrNv6C2Me-pjvXNx-uoh5OnTjDlOdzslJcE3Ci79ckLeH-9f1U7F5eXxerzaFZ8DGokLBJOdaVFKUjksJQW2dAM-RTY-Dlo6FUHmUpXZBc8F1VRrJDHoQzHC2IDfz3SH2H3tMo23r5LFpXIf9PtlSK2YUUxO8naGPfUoRgx1i3bp4sBTszwpWcPu7wkSvZloj4j-bu29Ul1UZ</recordid><startdate>19901001</startdate><enddate>19901001</enddate><creator>Bhasker, J.</creator><creator>Lee, H.-C.</creator><general>IEEE Computer Society</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19901001</creationdate><title>An optimizer for hardware synthesis</title><author>Bhasker, J. ; Lee, H.-C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c303t-be5364485b652a4660f7da50c4e3475f86a3ffbce628af84548b29639ec053943</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Circuit simulation</topic><topic>Circuit synthesis</topic><topic>Control systems</topic><topic>Costs</topic><topic>Hardware</topic><topic>Logic</topic><topic>Network synthesis</topic><topic>Parallel processing</topic><topic>Program processors</topic><topic>Testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Bhasker, J.</creatorcontrib><creatorcontrib>Lee, H.-C.</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE design & test of computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bhasker, J.</au><au>Lee, H.-C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An optimizer for hardware synthesis</atitle><jtitle>IEEE design & test of computers</jtitle><stitle>MDT</stitle><date>1990-10-01</date><risdate>1990</risdate><volume>7</volume><issue>5</issue><spage>20</spage><epage>36</epage><pages>20-36</pages><issn>0740-7475</issn><eissn>1558-1918</eissn><coden>IDTCEC</coden><abstract>A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. 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| ispartof | IEEE design & test of computers, 1990-10, Vol.7 (5), p.20-36 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Circuit simulation Circuit synthesis Control systems Costs Hardware Logic Network synthesis Parallel processing Program processors Testing |
| title | An optimizer for hardware synthesis |
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