An optimizer for hardware synthesis

An optimizer for hardware synthesis

A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decompos...

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Veröffentlicht in:IEEE design & test of computers 1990-10, Vol.7 (5), p.20-36
Hauptverfasser: Bhasker, J., Lee, H.-C.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit simulation
Circuit synthesis
Control systems
Costs
Hardware
Logic
Network synthesis
Parallel processing
Program processors
Testing
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Zusammenfassung:A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.< >
ISSN:0740-7475
1558-1918
DOI:10.1109/54.60604