Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM compri...

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Hauptverfasser: Okumura, S., Nakata, Y., Yanagida, K., Kagiyama, Y., Yoshimoto, S., Kawaguchi, H., Yoshimoto, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Logic gates
Microprocessors
Power measurement
Program processors
Random access memory
Redundancy
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Beschreibung
Zusammenfassung:This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2011.6055411