Low power and error resilient PN code acquisition filter via statistical error compensation

We present a 256-tap PN code acquisition filter in an 180nm CMOS process employing statistical system-level error compensation. Under voltage overscaling (VOS), near constant detection probability (P det ) above 90% with 5.8× reduction in energy is achieved at a supply voltage 27% below the point of first failure (PoFF) with an error rate (p e ) of 0.868. This is an improvement of 5.8× in energy-efficiency over conventional error free designs and 3.79× in energy-efficiency and 2170× in error tolerance over existing error tolerant designs.