A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC

A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC

This paper presents a 10b 30MS/s comparator-based two-step pipelined ADC that uses a comparator instead of an opamp to reach low-voltage and low-power operation with a rail-to-rail input. This implementation also incorporates a digital offset calibration scheme in the comparator. The prototype ADC,...

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Bibliographische Detailangaben
Hauptverfasser: Ho-Young Lee, Gubbins, D., Bumha Lee, Un-Ku Moon
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Accuracy
Arrays
Calibration
Capacitance
Capacitors
Prototypes
Switches
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Beschreibung
Zusammenfassung:This paper presents a 10b 30MS/s comparator-based two-step pipelined ADC that uses a comparator instead of an opamp to reach low-voltage and low-power operation with a rail-to-rail input. This implementation also incorporates a digital offset calibration scheme in the comparator. The prototype ADC, fabricated in a 0.13μm CMOS process, consumes 810μW at 0.7V supply and achieves 121fJ FOM at 10MHz input frequency.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2011.6055326