VHDL procedure for combinational divider

VHDL procedure for combinational divider

In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of impleme...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Fedra, Z., Kolouch, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Algorithm design and analysis
Delay
Digital systems
divider
Facsimile
Field programmable gate arrays
FPGA
implementation
procedure
static timing analysis
Table lookup
VHDL
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Beschreibung
Zusammenfassung:In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables.
DOI:10.1109/TSP.2011.6043687