A parallel-segmented architecture for low power Content-Addressable Memory

A novel, parallel-segmented architecture is proposed for low power Content Addressable Memory (CAM). The new architecture utilizes the par allegation concept to maintain the high searching operation while uses circuitry-level power reduction techniques to decrease power consumption. A 64×64 bits CAM is implemented using the new architecture and simulated using the BSIM4 public 65nm technology description at 1.0V voltage reference. The power estimation for the CAM using the new architecture is approximately 4.021mW as compare to the traditional CAM architecture, which consumes approximately 12.538mW when operating the memory at 800MHz clock speed.