A gain control Low Noise Amplifier for 24 GHz application

The Low Noise Amplifier is implemented in TSMC 0.18 μm 1P6M CMOS process. Circuit architecture of the first-stage uses the cascade stage to suppress Miller effect, the second-stage at the gate control of a group received more power, and then use voltage to control gain to achieve the advantages of s...

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Hauptverfasser: Pou-Tou Sun, Ssu-Chieh Chan, Ying-Jui Chuang
Format: Tagungsbericht
Sprache:eng
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Zusammenfassung:The Low Noise Amplifier is implemented in TSMC 0.18 μm 1P6M CMOS process. Circuit architecture of the first-stage uses the cascade stage to suppress Miller effect, the second-stage at the gate control of a group received more power, and then use voltage to control gain to achieve the advantages of savings in power consumption, amplifier measurement results shows the status of low-frequency. The gain is 5.1 dB, noise figure is 7 dB and the max control range is 4dB.
DOI:10.1109/CSQRWC.2011.6037034