Modeling the overshooting effect of multi-input gate in nanometer technologies

Modeling the overshooting effect of multi-input gate in nanometer technologies

With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooti...

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Hauptverfasser: Li Ding, Zhangcai Huang, Minglu Jiang, Kurokawa, Atsushi, Inoue, Yasuaki
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS integrated circuits
CMOS technology
Computational modeling
Integrated circuit modeling
Logic gates
MOS devices
Semiconductor device modeling
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Beschreibung
Zusammenfassung:With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2011.6026587