An ultra low voltage ultra high gain CMOS LNA using forward body biasing technique

A fully integrated 1.5 GHz low noise amplifier suitable for ultra-low voltage applications is designed and simulated in a standard 0.18μm CMOS technology. Using the folded cascode topology and forward body biasing technique, the proposed LNA works at a very low supply voltage and low power consumption. The proposed LNA has a power gain (S 21 ) of 22 dB with a noise figure of 1.9 dB, while consuming 2.5mW dc power with an ultra low supply voltage of 0.5 V.