Failure modes and robustness of SiC JFET transistors under current limiting operations
The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance...
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| creator | Bouarroudj-Berkani, M. Lefebvre, S. Othman, D. Sabrine, S. M. Khatir, Z. Salah, T. B. |
| description | The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance and saturation current are discussed. Finally, thermal simulation results are presented in order to understand and explain evolutions of some ageing indicators. |
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Finally, thermal simulation results are presented in order to understand and explain evolutions of some ageing indicators.</description><subject>Aging</subject><subject>Current limiter</subject><subject>JFET</subject><subject>JFETs</subject><subject>Junctions</subject><subject>Logic gates</subject><subject>Power semiconductor</subject><subject>Resistance</subject><subject>Robustness</subject><subject>Short circuit</subject><subject>Silicon carbide</subject><isbn>9781612841670</isbn><isbn>1612841678</isbn><isbn>9789075815153</isbn><isbn>9075815158</isbn><isbn>907581514X</isbn><isbn>9789075815146</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjstKxDAYhSMiKGOfwE1eoJA0t2YpxfHCwCwc3A5_mz8SaZMhSRe-vUU9m8OBj49zRRpresuM6rniSlz_bq5510uuDbslTSlfbIvWVlp7Rz72EOY1I12Sw0IhOprTuJYasRSaPH0PA33bP51ozRBLKDXlQtfoMNNpzRljpXNYQg3xk6YLZqghxXJPbjzMBZv_3pHT5hhe2sPx-XV4PLTBstqCAu7dKKWcjNOM4aS362bUqID1nnMJ2ptxAzqwwnCPwgrs7cSRT2J0Ykce_rQBEc-XHBbI32fNOiaUFj9Wsk4q</recordid><startdate>201108</startdate><enddate>201108</enddate><creator>Bouarroudj-Berkani, M.</creator><creator>Lefebvre, S.</creator><creator>Othman, D.</creator><creator>Sabrine, S. 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B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Failure modes and robustness of SiC JFET transistors under current limiting operations</atitle><btitle>Proceedings of the 2011 14th European Conference on Power Electronics and Applications</btitle><stitle>EPE</stitle><date>2011-08</date><risdate>2011</risdate><spage>1</spage><epage>10</epage><pages>1-10</pages><isbn>9781612841670</isbn><isbn>1612841678</isbn><eisbn>9789075815153</eisbn><eisbn>9075815158</eisbn><eisbn>907581514X</eisbn><eisbn>9789075815146</eisbn><abstract>The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance and saturation current are discussed. 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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Aging Current limiter JFET JFETs Junctions Logic gates Power semiconductor Resistance Robustness Short circuit Silicon carbide |
| title | Failure modes and robustness of SiC JFET transistors under current limiting operations |
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