Power consumption reduction for configuration SRAM of field programmable gate arrays

Power consumption reduction for configuration SRAM of field programmable gate arrays

This article describes a method of reducing power consumption for configuration SRAM cells. Modification of the SRAM cell is performed taking into account special characteristics of FPGA configuration memory. Characteristics of the cells are summarized.

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Bibliographische Detailangaben
Hauptverfasser: Matyushin, D. V., Kurganskii, S. I.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
asymmetric SRAM
Field programmable gate arrays
FPGA
Inverters
Leakage current
Noise
Random access memory
Threshold voltage
Transistors
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Beschreibung
Zusammenfassung:This article describes a method of reducing power consumption for configuration SRAM cells. Modification of the SRAM cell is performed taking into account special characteristics of FPGA configuration memory. Characteristics of the cells are summarized.
ISSN:1815-3712
DOI:10.1109/EDM.2011.6006917