Investigation of multi cell upset in sequential logic and validity of redundancy technique
Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitig...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 12 |
|---|---|
| container_issue | |
| container_start_page | 7 |
| container_title | |
| container_volume | |
| creator | Uemura, T. Kato, T. Matsuyama, H. Takahisa, K. Fukuda, M. Hatanaka, K. |
| description | Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies. |
| doi_str_mv | 10.1109/IOLTS.2011.5993803 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5993803</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5993803</ieee_id><sourcerecordid>5993803</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-3c13631db6d91691d82eea5021e530b8a75727bffdb091d91493a79348514f1a3</originalsourceid><addsrcrecordid>eNpVkMtOwzAURM1Loir5Adj4BxJ8YzvOXaKKR6VKXVA2bConvilGrlsap1L_niLKgtnM4szMYhi7BVEACLyfzmeL16IUAIVGlLWQZyxDU4PSxoDQGs7ZCFCVOSoBF_-YNJd_TGJ9zbK-_xRHVRUqDSP2Po176pNf2eQ3kW86vh5C8rylEPiw7SlxH3lPXwPF5G3gYbPyLbfR8b0N3vl0-CntyA3R2dgeeKL2I_pj_oZddTb0lJ18zN6eHheTl3w2f55OHma5B6NTLluQlQTXVA6hQnB1SWS1KIG0FE1tjTalabrONeJIERRKa1CqWoPqwMoxu_vd9US03O782u4Oy9NT8htgYliq</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Investigation of multi cell upset in sequential logic and validity of redundancy technique</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Uemura, T. ; Kato, T. ; Matsuyama, H. ; Takahisa, K. ; Fukuda, M. ; Hatanaka, K.</creator><creatorcontrib>Uemura, T. ; Kato, T. ; Matsuyama, H. ; Takahisa, K. ; Fukuda, M. ; Hatanaka, K.</creatorcontrib><description>Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.</description><identifier>ISSN: 1942-9398</identifier><identifier>ISBN: 9781457710537</identifier><identifier>ISBN: 1457710536</identifier><identifier>EISSN: 1942-9401</identifier><identifier>EISBN: 9781457710551</identifier><identifier>EISBN: 1457710560</identifier><identifier>EISBN: 9781457710568</identifier><identifier>EISBN: 1457710552</identifier><identifier>DOI: 10.1109/IOLTS.2011.5993803</identifier><language>eng</language><publisher>IEEE</publisher><subject>charge sharing ; flip-flop ; Flip-flops ; latch ; Latches ; Layout ; Logic gates ; MCU ; neutron ; Neutrons ; Redundancy ; sequential element ; soft error ; Tunneling magnetoresistance</subject><ispartof>2011 IEEE 17th International On-Line Testing Symposium, 2011, p.7-12</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5993803$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5993803$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Uemura, T.</creatorcontrib><creatorcontrib>Kato, T.</creatorcontrib><creatorcontrib>Matsuyama, H.</creatorcontrib><creatorcontrib>Takahisa, K.</creatorcontrib><creatorcontrib>Fukuda, M.</creatorcontrib><creatorcontrib>Hatanaka, K.</creatorcontrib><title>Investigation of multi cell upset in sequential logic and validity of redundancy technique</title><title>2011 IEEE 17th International On-Line Testing Symposium</title><addtitle>IOLTS</addtitle><description>Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.</description><subject>charge sharing</subject><subject>flip-flop</subject><subject>Flip-flops</subject><subject>latch</subject><subject>Latches</subject><subject>Layout</subject><subject>Logic gates</subject><subject>MCU</subject><subject>neutron</subject><subject>Neutrons</subject><subject>Redundancy</subject><subject>sequential element</subject><subject>soft error</subject><subject>Tunneling magnetoresistance</subject><issn>1942-9398</issn><issn>1942-9401</issn><isbn>9781457710537</isbn><isbn>1457710536</isbn><isbn>9781457710551</isbn><isbn>1457710560</isbn><isbn>9781457710568</isbn><isbn>1457710552</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtOwzAURM1Loir5Adj4BxJ8YzvOXaKKR6VKXVA2bConvilGrlsap1L_niLKgtnM4szMYhi7BVEACLyfzmeL16IUAIVGlLWQZyxDU4PSxoDQGs7ZCFCVOSoBF_-YNJd_TGJ9zbK-_xRHVRUqDSP2Po176pNf2eQ3kW86vh5C8rylEPiw7SlxH3lPXwPF5G3gYbPyLbfR8b0N3vl0-CntyA3R2dgeeKL2I_pj_oZddTb0lJ18zN6eHheTl3w2f55OHma5B6NTLluQlQTXVA6hQnB1SWS1KIG0FE1tjTalabrONeJIERRKa1CqWoPqwMoxu_vd9US03O782u4Oy9NT8htgYliq</recordid><startdate>201107</startdate><enddate>201107</enddate><creator>Uemura, T.</creator><creator>Kato, T.</creator><creator>Matsuyama, H.</creator><creator>Takahisa, K.</creator><creator>Fukuda, M.</creator><creator>Hatanaka, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201107</creationdate><title>Investigation of multi cell upset in sequential logic and validity of redundancy technique</title><author>Uemura, T. ; Kato, T. ; Matsuyama, H. ; Takahisa, K. ; Fukuda, M. ; Hatanaka, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-3c13631db6d91691d82eea5021e530b8a75727bffdb091d91493a79348514f1a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>charge sharing</topic><topic>flip-flop</topic><topic>Flip-flops</topic><topic>latch</topic><topic>Latches</topic><topic>Layout</topic><topic>Logic gates</topic><topic>MCU</topic><topic>neutron</topic><topic>Neutrons</topic><topic>Redundancy</topic><topic>sequential element</topic><topic>soft error</topic><topic>Tunneling magnetoresistance</topic><toplevel>online_resources</toplevel><creatorcontrib>Uemura, T.</creatorcontrib><creatorcontrib>Kato, T.</creatorcontrib><creatorcontrib>Matsuyama, H.</creatorcontrib><creatorcontrib>Takahisa, K.</creatorcontrib><creatorcontrib>Fukuda, M.</creatorcontrib><creatorcontrib>Hatanaka, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Uemura, T.</au><au>Kato, T.</au><au>Matsuyama, H.</au><au>Takahisa, K.</au><au>Fukuda, M.</au><au>Hatanaka, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Investigation of multi cell upset in sequential logic and validity of redundancy technique</atitle><btitle>2011 IEEE 17th International On-Line Testing Symposium</btitle><stitle>IOLTS</stitle><date>2011-07</date><risdate>2011</risdate><spage>7</spage><epage>12</epage><pages>7-12</pages><issn>1942-9398</issn><eissn>1942-9401</eissn><isbn>9781457710537</isbn><isbn>1457710536</isbn><eisbn>9781457710551</eisbn><eisbn>1457710560</eisbn><eisbn>9781457710568</eisbn><eisbn>1457710552</eisbn><abstract>Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.</abstract><pub>IEEE</pub><doi>10.1109/IOLTS.2011.5993803</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1942-9398 |
| ispartof | 2011 IEEE 17th International On-Line Testing Symposium, 2011, p.7-12 |
| issn | 1942-9398 1942-9401 |
| language | eng |
| recordid | cdi_ieee_primary_5993803 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | charge sharing flip-flop Flip-flops latch Latches Layout Logic gates MCU neutron Neutrons Redundancy sequential element soft error Tunneling magnetoresistance |
| title | Investigation of multi cell upset in sequential logic and validity of redundancy technique |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T16%3A12%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Investigation%20of%20multi%20cell%20upset%20in%20sequential%20logic%20and%20validity%20of%20redundancy%20technique&rft.btitle=2011%20IEEE%2017th%20International%20On-Line%20Testing%20Symposium&rft.au=Uemura,%20T.&rft.date=2011-07&rft.spage=7&rft.epage=12&rft.pages=7-12&rft.issn=1942-9398&rft.eissn=1942-9401&rft.isbn=9781457710537&rft.isbn_list=1457710536&rft_id=info:doi/10.1109/IOLTS.2011.5993803&rft_dat=%3Cieee_6IE%3E5993803%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781457710551&rft.eisbn_list=1457710560&rft.eisbn_list=9781457710568&rft.eisbn_list=1457710552&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5993803&rfr_iscdi=true |