Investigation of multi cell upset in sequential logic and validity of redundancy technique

Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.