Leakage-aware redundancy for reliable sub-threshold memories

Leakage-aware redundancy for reliable sub-threshold memories

In this work, we are the first to consider the optimization of sub-threshold stand-by VDD while simultaneously considering memory yield and redundant row/column usage. We propose a fast, optimal fault-repair analysis framework that is 200--600% faster than previous works and show that leakage can be...

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Bibliographische Detailangaben
Hauptverfasser: Kim, Seokjoong, Guthaus, Matthew
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Arrays
Circuit faults
leakage
Maintenance engineering
Manufacturing
Random access memory
Redundancy
Sub-threshold SRAM
yield enhancement
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Beschreibung
Zusammenfassung:In this work, we are the first to consider the optimization of sub-threshold stand-by VDD while simultaneously considering memory yield and redundant row/column usage. We propose a fast, optimal fault-repair analysis framework that is 200--600% faster than previous works and show that leakage can be reduced 10--14% using redundancy without sacrificing yield.
ISSN:0738-100X
DOI:10.1145/2024724.2024826