Integration of a plasma doping PULSION® process into a fully depleted SOI transistor flow chart

Integration of a plasma doping PULSION® process into a fully depleted SOI transistor flow chart

In this paper we discuss the integration of plasma doping into a Fully Depleted SOI CMOS process flow (sub-10 nm top Si layer). The compatibility of PD with patterns (charging effects) has been studied as well as the Selective Epitaxial Growth (SEG) performed after the source/drain extension implant...

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Bibliographische Detailangaben
Hauptverfasser: Duchaine, J., Gonzatti, F., Torregrosa, F., Etienne, H., Felch, S., Milesi, F., Yckache, K., Spiegel, Y., Claverie, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Doping
Implants
Ion implantation
Plasmas
Resists
Scanning electron microscopy
Silicon
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Zusammenfassung:In this paper we discuss the integration of plasma doping into a Fully Depleted SOI CMOS process flow (sub-10 nm top Si layer). The compatibility of PD with patterns (charging effects) has been studied as well as the Selective Epitaxial Growth (SEG) performed after the source/drain extension implantations to thicken these regions prior to silicidation.
DOI:10.1109/IWJT.2011.5970001