System synthesis from AADL using Polychrony

The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use the high-level modeling, domain-specific, language AADL for system-level co-design; use the formal framework Polychrony, based on the synchronous language Signal, for analysis, validation and synthesis. According to SIGNAL's polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony.