Impact of TSV proximity on 45nm CMOS devices in wafer level

Impact of TSV proximity on 45nm CMOS devices in wafer level

Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using `via middle' process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Most...

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Hauptverfasser: Sungdong Cho, Sinwoo Kang, Kangwook Park, Jaechul Kim, Kiyoung Yun, Kisoon Bae, Woon Seob Lee, Sangwook Ji, Eunji Kim, Jangho Kim, Park, Y. L., Jung, E. S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS integrated circuits
Electric variables measurement
Logic gates
Performance evaluation
Stress
Threshold voltage
Through-silicon vias
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Beschreibung
Zusammenfassung:Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using `via middle' process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Mostly the device performance change due to TSV is observed in less than 2um distance but the change is less than 2% in maximum. Also discrepancy between theory and real data on TSV impact was identified.
ISSN:2380-632X
2380-6338
DOI:10.1109/IITC.2011.5940326