VLSI implementation of a modular and programmable neural architecture

A mixed-signal VLSI chip architecture for multi-layer feedforward neural network implementation with digitally programmable synapses is presented. The chip realizes a fully connected single-layer network, configurable as a 48 input/48 output neurons with 2304 5-bit synapses or as a 24 input/24 output neurons with 1152 9-bit synapses. This single layer network can be reconfigured as a multi-layer network. Another important chip feature is the possibility of connecting the chips in order to obtain a more complex multi-layer neural network. The core of the authors' architecture is a very efficient circuit block, "distributed sigmoid-synapse", that they used to implement each of the 2304 5-bit synapses included in the programmable neural network. A prototyping chip, including all the basic block of neural architecture, is now processed by ES2 with 1.0 /spl mu/m CMOS technology. Finally, the authors report the architecture of a possible system for the evaluation of the VLSI chip performances. Parameter mismatches present in the chip were considered to be not critical because it is possible to account them during the training of the neural network by using a special chip-in-the-loop training algorithm. The authors planned to use this chip in pattern recognition and image processing applications.