A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture
A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1988-10, Vol.23 (5), p.1104-1112 |
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| container_end_page | 1112 |
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| container_issue | 5 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 23 |
| creator | Inoue, M. Yamada, T. Kotani, H. Yamauchi, H. Fujiwara, A. Matsushima, J. Akamatsu, H. Fukumoto, M. Kubota, M. Nakao, I. Aoi, N. Fuse, G. Ogawa, S. Odanaka, S. Ueno, A. Yamamoto, H. |
| description | A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time.< > |
| doi_str_mv | 10.1109/4.5931 |
| format | Article |
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It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.5931</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Bismuth ; Capacitance ; Capacitors ; CMOS technology ; DRAM chips ; Electronics ; Exact sciences and technology ; Fuses ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Packaging ; Random access memory ; Semiconductor device measurement ; Semiconductor device noise ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><ispartof>IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1104-1112</ispartof><rights>1990 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c292t-36fccef338df3aa988f5738fbe3bee03f57d0110101cdc75878934f0031de8f73</citedby><cites>FETCH-LOGICAL-c292t-36fccef338df3aa988f5738fbe3bee03f57d0110101cdc75878934f0031de8f73</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5931$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5931$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=6914851$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Inoue, M.</creatorcontrib><creatorcontrib>Yamada, T.</creatorcontrib><creatorcontrib>Kotani, H.</creatorcontrib><creatorcontrib>Yamauchi, H.</creatorcontrib><creatorcontrib>Fujiwara, A.</creatorcontrib><creatorcontrib>Matsushima, J.</creatorcontrib><creatorcontrib>Akamatsu, H.</creatorcontrib><creatorcontrib>Fukumoto, M.</creatorcontrib><creatorcontrib>Kubota, M.</creatorcontrib><creatorcontrib>Nakao, I.</creatorcontrib><creatorcontrib>Aoi, N.</creatorcontrib><creatorcontrib>Fuse, G.</creatorcontrib><creatorcontrib>Ogawa, S.</creatorcontrib><creatorcontrib>Odanaka, S.</creatorcontrib><creatorcontrib>Ueno, A.</creatorcontrib><creatorcontrib>Yamamoto, H.</creatorcontrib><title>A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time.< ></description><subject>Applied sciences</subject><subject>Bismuth</subject><subject>Capacitance</subject><subject>Capacitors</subject><subject>CMOS technology</subject><subject>DRAM chips</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Fuses</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Packaging</subject><subject>Random access memory</subject><subject>Semiconductor device measurement</subject><subject>Semiconductor device noise</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Inoue, M.</creatorcontrib><creatorcontrib>Yamada, T.</creatorcontrib><creatorcontrib>Kotani, H.</creatorcontrib><creatorcontrib>Yamauchi, H.</creatorcontrib><creatorcontrib>Fujiwara, A.</creatorcontrib><creatorcontrib>Matsushima, J.</creatorcontrib><creatorcontrib>Akamatsu, H.</creatorcontrib><creatorcontrib>Fukumoto, M.</creatorcontrib><creatorcontrib>Kubota, M.</creatorcontrib><creatorcontrib>Nakao, I.</creatorcontrib><creatorcontrib>Aoi, N.</creatorcontrib><creatorcontrib>Fuse, G.</creatorcontrib><creatorcontrib>Ogawa, S.</creatorcontrib><creatorcontrib>Odanaka, S.</creatorcontrib><creatorcontrib>Ueno, A.</creatorcontrib><creatorcontrib>Yamamoto, H.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>METADEX</collection><collection>Materials Research Database</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Inoue, M.</au><au>Yamada, T.</au><au>Kotani, H.</au><au>Yamauchi, H.</au><au>Fujiwara, A.</au><au>Matsushima, J.</au><au>Akamatsu, H.</au><au>Fukumoto, M.</au><au>Kubota, M.</au><au>Nakao, I.</au><au>Aoi, N.</au><au>Fuse, G.</au><au>Ogawa, S.</au><au>Odanaka, S.</au><au>Ueno, A.</au><au>Yamamoto, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1988-10-01</date><risdate>1988</risdate><volume>23</volume><issue>5</issue><spage>1104</spage><epage>1112</epage><pages>1104-1112</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.5931</doi><tpages>9</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1104-1112 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Bismuth Capacitance Capacitors CMOS technology DRAM chips Electronics Exact sciences and technology Fuses Integrated circuits Integrated circuits by function (including memories and processors) Packaging Random access memory Semiconductor device measurement Semiconductor device noise Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture |
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