A 150-mW dynamic power 10-ns 22V10 programmable logic device (PLD)

The authors describe a PLD architecture that eliminates sense amp circuitry in a 22V10 device, resulting in zero quiescent current and dynamic power levels that are one quarter that of previous architectures while still achieving state-of-the-art switching speed and 100% 22V10 functionality. The low...

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Bibliographische Detailangaben
Hauptverfasser:	Holly, P., Sutton, T., Dandas Tang, Wanhao Li, Butler, P., Zlotnick, F., Mao, R., Vinh, J., Kaplinsky, C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits CMOS technology Decoding Energy consumption EPROM Logic arrays Logic devices Macrocell networks Programmable logic arrays Programmable logic devices
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Beschreibung
Zusammenfassung:	The authors describe a PLD architecture that eliminates sense amp circuitry in a 22V10 device, resulting in zero quiescent current and dynamic power levels that are one quarter that of previous architectures while still achieving state-of-the-art switching speed and 100% 22V10 functionality. The low power and ability to operate at 3 V make this architecture suitable for battery-powered applications. The MC22V10ST is implemented using a multifunction logic array architecture consisting of two logic planes followed by a macrocell. The MC22V10ST emulates all 22V10 device features with equivalent speed. Specific architectural enhancements are detailed and simulation results are shown.
DOI:	10.1109/CICC.1993.590579