A versatile 30V analog CMOS process in a 0.18μm technology for power management application

A versatile 30V analog CMOS process in a 0.18μm technology for power management application

A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off perform...

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Hauptverfasser: Yong-Keon Choi, Il-Yong Park, Hyun-Chol Lim, Mi-Young Kim, Chul-Jin Yoon, Nam-Joo Kim, Kwang-Dong Yoo, Hutter, L. N.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog circuits
CMOS integrated circuits
CMOS technology
EPROM
Logic gates
Noise
Transistors
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Zusammenfassung:A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2011.5890830