A 16 b 100 k sample/s 2.7 V 25 mW ADC/DSP/DAC-based analog signal processor in 0.8 /spl mu/m CMOS

A 16 b 100 k sample/s 2.7 V 25 mW ADC/DSP/DAC-based analog signal processor in 0.8 /spl mu/m CMOS

The 0.8/spl mu/m CMOS signal processor described combines a low-noise analog front-end and reference, 16b ADC/DAC, and 16b DSP optimized for filter applications. With 25mW typical power consumption at 100kSample/s (3mW for ADC/DAC) it can be programmed for high-order analog filtering and other signa...

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Bibliographische Detailangaben
Hauptverfasser: Dedic, I.J., Amos, N.C., King, M.J., Schofield, W.G., Kemp, A.K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
CMOS process
Digital signal processing
Energy consumption
Filtering
Filters
Read-write memory
Signal processing
Switches
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Beschreibung
Zusammenfassung:The 0.8/spl mu/m CMOS signal processor described combines a low-noise analog front-end and reference, 16b ADC/DAC, and 16b DSP optimized for filter applications. With 25mW typical power consumption at 100kSample/s (3mW for ADC/DAC) it can be programmed for high-order analog filtering and other signal processing functions with 80dB typical SNR.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1997.585278