FPGA-based fine grain processor array design considerations

Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal "jigsaw tessellated" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based...

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Bibliographische Detailangaben
Hauptverfasser:	Erenyi, I., Vassanyi, I.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Cost function Field programmable gate arrays Hardware Process design Programmable logic arrays Routing Systolic arrays Tiles Transforms
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Beschreibung
Zusammenfassung:	Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal "jigsaw tessellated" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.
DOI:	10.1109/ICECS.1996.584448