Rapid layout synthesis for analog VLSI

Rapid layout synthesis for analog VLSI

A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, a design rule correct layout is generated. The complete system has been tested by synthes...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Walczowski, L.T., Waller, W.A.J., Nalbantis, D., Shi, K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit simulation
Circuit synthesis
Circuit testing
CMOS technology
Laboratories
Object oriented modeling
Operational amplifiers
Space exploration
System testing
Very large scale integration
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Beschreibung
Zusammenfassung:A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, a design rule correct layout is generated. The complete system has been tested by synthesizing op amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters.
DOI:10.1109/ICECS.1996.582845