Gate-driven 3.3V ESD clamp using 1.8V transistors

Gate-driven 3.3V ESD clamp using 1.8V transistors

A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-ti...

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Bibliographische Detailangaben
Hauptverfasser: Guang-Cheng Wang, Chia-Hui Chen, Wen-Hsin Huang, Kuo-Ji Chen, Ming-Hsiang Song, Ta-Pen Guo
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clamps
Electrostatic discharge
gate oxide over-stress
gate-driven
human-body model (HBM)
Logic gates
machine model (MM)
Rails
Resistors
System-on-a-chip
Transistors
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Beschreibung
Zusammenfassung:A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/-200mA current triggering and 4.95V (1.5 × VDD) over-voltage test.
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2011.5783234