A fast CRAM SEU error detection scheme for FPGAs
This paper proposes a scheme that can detect SEU errors occurring in an FPGA configuration SRAM cell (CRAM) in a time-efficient manner (>;40X faster or
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creator | Jong Kiun Kiet Tan Jun Pin Ang Boon Jin |
description | This paper proposes a scheme that can detect SEU errors occurring in an FPGA configuration SRAM cell (CRAM) in a time-efficient manner (>;40X faster or |
doi_str_mv | 10.1109/APCCAS.2010.5775097 |
format | Conference Proceeding |
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The concept and design implementation of the proposed scheme is described in detail. This is a low-cost solution as most of the implementation reuses existing circuits. In addition, the benefits of the proposed schemes are discussed.</description><identifier>ISBN: 142447454X</identifier><identifier>ISBN: 9781424474547</identifier><identifier>EISBN: 9781424474561</identifier><identifier>EISBN: 1424474558</identifier><identifier>EISBN: 1424474566</identifier><identifier>EISBN: 9781424474554</identifier><identifier>DOI: 10.1109/APCCAS.2010.5775097</identifier><language>eng</language><publisher>IEEE</publisher><subject>CRAM ; Error Detection ; Field programmable gate arrays ; FPGA ; LFSR ; MISR ; SEU</subject><ispartof>2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010, p.995-998</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5775097$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5775097$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jong Kiun Kiet</creatorcontrib><creatorcontrib>Tan Jun Pin</creatorcontrib><creatorcontrib>Ang Boon Jin</creatorcontrib><title>A fast CRAM SEU error detection scheme for FPGAs</title><title>2010 IEEE Asia Pacific Conference on Circuits and Systems</title><addtitle>APCCAS</addtitle><description>This paper proposes a scheme that can detect SEU errors occurring in an FPGA configuration SRAM cell (CRAM) in a time-efficient manner (>;40X faster or<;2 ms). The concept and design implementation of the proposed scheme is described in detail. This is a low-cost solution as most of the implementation reuses existing circuits. In addition, the benefits of the proposed schemes are discussed.</description><subject>CRAM</subject><subject>Error Detection</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>LFSR</subject><subject>MISR</subject><subject>SEU</subject><isbn>142447454X</isbn><isbn>9781424474547</isbn><isbn>9781424474561</isbn><isbn>1424474558</isbn><isbn>1424474566</isbn><isbn>9781424474554</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j81KAzEUhSMiqHWeoJu8wNSb3ztZhtBWoWKxFdyVJHMHR6yVyWx8ewesZ_NxvsWBw9hcwEIIcPd-G4LfLSRMwiAacHjBKoeN0FJr1MaKS3b7X_TbNatK-YAp1jYNyhsGnnexjDy8-Ce-W75yGobTwFsaKY_96YuX_E5H4t0kV9u1L3fsqoufhaozZ2y_Wu7DQ715Xj8Gv6l7B2OdTBYoO0UWUebUoqYEmQixi6bNiUg6AcrpmFSELBuTNEZyFgw11rZqxuZ_sz0RHb6H_hiHn8P5o_oF2lFDuA</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>Jong Kiun Kiet</creator><creator>Tan Jun Pin</creator><creator>Ang Boon Jin</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201012</creationdate><title>A fast CRAM SEU error detection scheme for FPGAs</title><author>Jong Kiun Kiet ; Tan Jun Pin ; Ang Boon Jin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-b5c172f3e6772cbd74eb0cee77fa5dcbee2910394ab3a0c285b47ae9605e866d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>CRAM</topic><topic>Error Detection</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>LFSR</topic><topic>MISR</topic><topic>SEU</topic><toplevel>online_resources</toplevel><creatorcontrib>Jong Kiun Kiet</creatorcontrib><creatorcontrib>Tan Jun Pin</creatorcontrib><creatorcontrib>Ang Boon Jin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jong Kiun Kiet</au><au>Tan Jun Pin</au><au>Ang Boon Jin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A fast CRAM SEU error detection scheme for FPGAs</atitle><btitle>2010 IEEE Asia Pacific Conference on Circuits and Systems</btitle><stitle>APCCAS</stitle><date>2010-12</date><risdate>2010</risdate><spage>995</spage><epage>998</epage><pages>995-998</pages><isbn>142447454X</isbn><isbn>9781424474547</isbn><eisbn>9781424474561</eisbn><eisbn>1424474558</eisbn><eisbn>1424474566</eisbn><eisbn>9781424474554</eisbn><abstract>This paper proposes a scheme that can detect SEU errors occurring in an FPGA configuration SRAM cell (CRAM) in a time-efficient manner (>;40X faster or<;2 ms). The concept and design implementation of the proposed scheme is described in detail. This is a low-cost solution as most of the implementation reuses existing circuits. In addition, the benefits of the proposed schemes are discussed.</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2010.5775097</doi><tpages>4</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | CRAM Error Detection Field programmable gate arrays FPGA LFSR MISR SEU |
title | A fast CRAM SEU error detection scheme for FPGAs |
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