An energy-efficient successive approximation register analog to digital converter in 180nm

An energy-efficient successive approximation register analog to digital converter in 180nm

This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simul...

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Bibliographische Detailangaben
Hauptverfasser: Kuntz, Taimur Gibran Rabuske, Nooshabadi, Saeid
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Approximation methods
Arrays
Capacitors
CMOS integrated circuits
Power demand
Topology
Voltage control
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Beschreibung
Zusammenfassung:This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations. This FOM is close to reference designs reported in 90nm.
DOI:10.1109/APCCAS.2010.5774967