Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver
A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demon...
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| Veröffentlicht in: | IEEE transactions on microwave theory and techniques 2011-07, Vol.59 (7), p.1832-1839 |
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| container_title | IEEE transactions on microwave theory and techniques |
| container_volume | 59 |
| creator | Kyujin Oh Yanping Ding Kenneth, K. O. |
| description | A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demonstrated. The phase noise of the 24-GHz LO signal is -89 dBc/Hz at 1-MHz offset for a 400-Mb/s pseudo random binary sequence (PRBS) 2 31 - 1 input. This first report of phase noise for a CDR is more than acceptable for amplitude shift-keying wireless communication systems with a square-law detector that is immune to the phase noise. The jitter of 400-MHz recovered clock is 2.6-ps rms (0.1% UI) for a PRBS 2 31 - 1 input. The jitter performance is the best among the similar data rate (~400 Mb/s) CDRs. The CDR bit error rate is less than 10 -13 . |
| doi_str_mv | 10.1109/TMTT.2011.2144992 |
| format | Article |
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O.</creator><creatorcontrib>Kyujin Oh ; Yanping Ding ; Kenneth, K. O.</creatorcontrib><description>A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demonstrated. The phase noise of the 24-GHz LO signal is -89 dBc/Hz at 1-MHz offset for a 400-Mb/s pseudo random binary sequence (PRBS) 2 31 - 1 input. This first report of phase noise for a CDR is more than acceptable for amplitude shift-keying wireless communication systems with a square-law detector that is immune to the phase noise. The jitter of 400-MHz recovered clock is 2.6-ps rms (0.1% UI) for a PRBS 2 31 - 1 input. The jitter performance is the best among the similar data rate (~400 Mb/s) CDRs. The CDR bit error rate is less than 10 -13 .</description><identifier>ISSN: 0018-9480</identifier><identifier>EISSN: 1557-9670</identifier><identifier>DOI: 10.1109/TMTT.2011.2144992</identifier><identifier>CODEN: IETMAB</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Amplitude shift keying (ASK) ; Applied sciences ; Capacitors ; Circuit properties ; Circuits ; clock and data recovery (CDR) ; Clocks ; Data recovery ; Detectors ; Digital broadcasting ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Frequency conversion ; Jitter ; local oscillator (LO) generation ; Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits ; Noise ; Oscillations ; Oscillators, resonators, synthetizers ; Phase noise ; Radiocommunications ; Sampling ; Signal convertors ; Telecommunications ; Telecommunications and information theory ; transceiver ; Transmitters. Receivers ; Tuning ; Voltage-controlled oscillators ; Wireless communications</subject><ispartof>IEEE transactions on microwave theory and techniques, 2011-07, Vol.59 (7), p.1832-1839</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jul 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c354t-1606803128ddc3a0d4181da4e2076d11f14f2268de08e6c337efb0d0a7a465703</citedby><cites>FETCH-LOGICAL-c354t-1606803128ddc3a0d4181da4e2076d11f14f2268de08e6c337efb0d0a7a465703</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5772944$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5772944$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24392268$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kyujin Oh</creatorcontrib><creatorcontrib>Yanping Ding</creatorcontrib><creatorcontrib>Kenneth, K. O.</creatorcontrib><title>Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver</title><title>IEEE transactions on microwave theory and techniques</title><addtitle>TMTT</addtitle><description>A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demonstrated. The phase noise of the 24-GHz LO signal is -89 dBc/Hz at 1-MHz offset for a 400-Mb/s pseudo random binary sequence (PRBS) 2 31 - 1 input. This first report of phase noise for a CDR is more than acceptable for amplitude shift-keying wireless communication systems with a square-law detector that is immune to the phase noise. The jitter of 400-MHz recovered clock is 2.6-ps rms (0.1% UI) for a PRBS 2 31 - 1 input. The jitter performance is the best among the similar data rate (~400 Mb/s) CDRs. The CDR bit error rate is less than 10 -13 .</description><subject>Amplitude shift keying (ASK)</subject><subject>Applied sciences</subject><subject>Capacitors</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>clock and data recovery (CDR)</subject><subject>Clocks</subject><subject>Data recovery</subject><subject>Detectors</subject><subject>Digital broadcasting</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Frequency conversion</subject><subject>Jitter</subject><subject>local oscillator (LO) generation</subject><subject>Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits</subject><subject>Noise</subject><subject>Oscillations</subject><subject>Oscillators, resonators, synthetizers</subject><subject>Phase noise</subject><subject>Radiocommunications</subject><subject>Sampling</subject><subject>Signal convertors</subject><subject>Telecommunications</subject><subject>Telecommunications and information theory</subject><subject>transceiver</subject><subject>Transmitters. Receivers</subject><subject>Tuning</subject><subject>Voltage-controlled oscillators</subject><subject>Wireless communications</subject><issn>0018-9480</issn><issn>1557-9670</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1r3DAQhkVpoNs0P6D0IgqlJ29nZFkfx-I0m8KGQHCgN6FK4-LUsVPJW9j--mrZJYechmGed0Z6GHuPsEYE-6W76bq1AMS1QCmtFa_YCptGV1ZpeM1WAGgqKw28YW9zfiitbMCs2I8bSr8o8nacw29-6RfP7yjMfyntuZ8iF7LaXP_j21u-oYmSX4Z54u2Qwm5YeD8n3qZ9Xvw4Us68S37KIdNQ4u_YWe_HTBenes7ur7517XW1vd18b79uq1A3cqlQgTJQozAxhtpDlGgwekkCtIqIPcpeCGUigSEV6lpT_xMieO2lajTU5-zzce9Tmv_sKC_ucciBxtFPNO-ys4CqgI0p5McX5MO8S1N5nDNaiXJX2ALhEQppzjlR757S8OjT3iG4g2l3MO0Opt3JdMl8Oi32OfixLxbCkJ-DQtb28IXCfThyAxE9jxuthZWy_g_jA4TD</recordid><startdate>20110701</startdate><enddate>20110701</enddate><creator>Kyujin Oh</creator><creator>Yanping Ding</creator><creator>Kenneth, K. O.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20110701</creationdate><title>Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver</title><author>Kyujin Oh ; Yanping Ding ; Kenneth, K. O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c354t-1606803128ddc3a0d4181da4e2076d11f14f2268de08e6c337efb0d0a7a465703</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Amplitude shift keying (ASK)</topic><topic>Applied sciences</topic><topic>Capacitors</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>clock and data recovery (CDR)</topic><topic>Clocks</topic><topic>Data recovery</topic><topic>Detectors</topic><topic>Digital broadcasting</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Frequency conversion</topic><topic>Jitter</topic><topic>local oscillator (LO) generation</topic><topic>Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits</topic><topic>Noise</topic><topic>Oscillations</topic><topic>Oscillators, resonators, synthetizers</topic><topic>Phase noise</topic><topic>Radiocommunications</topic><topic>Sampling</topic><topic>Signal convertors</topic><topic>Telecommunications</topic><topic>Telecommunications and information theory</topic><topic>transceiver</topic><topic>Transmitters. Receivers</topic><topic>Tuning</topic><topic>Voltage-controlled oscillators</topic><topic>Wireless communications</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kyujin Oh</creatorcontrib><creatorcontrib>Yanping Ding</creatorcontrib><creatorcontrib>Kenneth, K. O.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on microwave theory and techniques</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kyujin Oh</au><au>Yanping Ding</au><au>Kenneth, K. O.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver</atitle><jtitle>IEEE transactions on microwave theory and techniques</jtitle><stitle>TMTT</stitle><date>2011-07-01</date><risdate>2011</risdate><volume>59</volume><issue>7</issue><spage>1832</spage><epage>1839</epage><pages>1832-1839</pages><issn>0018-9480</issn><eissn>1557-9670</eissn><coden>IETMAB</coden><abstract>A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demonstrated. The phase noise of the 24-GHz LO signal is -89 dBc/Hz at 1-MHz offset for a 400-Mb/s pseudo random binary sequence (PRBS) 2 31 - 1 input. This first report of phase noise for a CDR is more than acceptable for amplitude shift-keying wireless communication systems with a square-law detector that is immune to the phase noise. The jitter of 400-MHz recovered clock is 2.6-ps rms (0.1% UI) for a PRBS 2 31 - 1 input. The jitter performance is the best among the similar data rate (~400 Mb/s) CDRs. The CDR bit error rate is less than 10 -13 .</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TMTT.2011.2144992</doi><tpages>8</tpages></addata></record> |
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| ispartof | IEEE transactions on microwave theory and techniques, 2011-07, Vol.59 (7), p.1832-1839 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Amplitude shift keying (ASK) Applied sciences Capacitors Circuit properties Circuits clock and data recovery (CDR) Clocks Data recovery Detectors Digital broadcasting Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Frequency conversion Jitter local oscillator (LO) generation Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits Noise Oscillations Oscillators, resonators, synthetizers Phase noise Radiocommunications Sampling Signal convertors Telecommunications Telecommunications and information theory transceiver Transmitters. Receivers Tuning Voltage-controlled oscillators Wireless communications |
| title | Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver |
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