Low level image processing operators on FPGA: implementation examples and performance evaluation

Low level image processing operators on FPGA: implementation examples and performance evaluation

This work deals with evaluation of hardware implementations of image processing algorithms for real time applications, using SRAM based field-programmable gate arrays. We discuss a generic architectural model adapted to this domain and to the technology characteristics. A method to evaluate the area...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Alves de Barros, M., Akil, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit testing
Computer architecture
Costs
Field programmable gate arrays
Hardware
Image processing
Logic testing
Performance evaluation
System testing
Timing
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Beschreibung
Zusammenfassung:This work deals with evaluation of hardware implementations of image processing algorithms for real time applications, using SRAM based field-programmable gate arrays. We discuss a generic architectural model adapted to this domain and to the technology characteristics. A method to evaluate the area costs and timing performances of architectures implemented on such a model is presented. A feasibility study of a pre-processing chain in an image-recognition system is presented.
DOI:10.1109/ICPR.1994.577173