F6: High-speed transceivers: Standards, challenges, and future

Multi-Gbps transceivers have evolved from what were once exotic special-purpose cells to ubiquitous building blocks that are expected to function as the glue bet ween critical compute, communications, and storage elements. As such they are expected to function flawlessly, interoperate cleanly, and consume little power, area, and system design mindshare. As part of the 'commoditizing' of transceivers, the pressure to achieve multiple standards compliance from individual designs has increased dramatically no longer are ASIC or system designers content with a single PHY for a single standard. The consequential impact on the design space means link designers must often 'right size' a swiss-army-knife design including power and area optimization; you don't want too many or too few 'blades'. Sometimes conflicting standards requirements can make customization and optimization a real challenge in this space. Jared Zerbe of Rambus will review some of the fundamental transceiver challenges and techniques used to address them, including a discussion of the impact of multi-standard compliance on the transceiver design effort and ultimate performance. Following this, Thomas Toifl of IBM will discuss the design challenges and solutions to data rates above 20Gb/s. Main challenges are achieving the required bandwidth with full ESD protection, the DFE loop timing, and overall design complexity. Marcus van lerssel of Snowbush IP will discuss implementation challenges and the benefits of a multi-standard PHY supporting Ethernet/PCIe/SATA/USB. Takeshi Horiefrom Fujitsu will present Ethernet standards and the technologies required to realize 10GB serial backplane transfer for 10GB Ethernet. When it comes to buidling standards compliant PHYs, IP providers face challenges that arise from the need to proliferate the design across many process geome tries/foundries and also from the large variability in customer's expertise in package design and signal integrity analysis. Dan Weinlader of Synopsys will discuss how standards influence these challenges. The main focus of standards over the last few years has understandably been on addressing the bandwidth curve. The need to address the rising power struggle of SoCs is usually recognized, but limited to simple power targets. The final two presentations in this forum will focus on energy efficiency by Fulvio Spagna of Intel and on low-power solutions by Anthony Sanders of Lantiq.