A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life an...

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Hauptverfasser: Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Clocks
CMOS technology
Delay
Random access memory
Voltage control
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creator Hyun-Woo Lee
Ki-Han Kim
Young-Kyoung Choi
Ju-Hwan Shon
Nak-Kyu Park
Kwan-Weon Kim
Chulwoo Kim
Young-Jung Choi
Byong-Tae Chung
description This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.
doi_str_mv 10.1109/ISSCC.2011.5746416
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5746416</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5746416</ieee_id><sourcerecordid>5746416</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-26b1fb0b9790e61d3bd23a9d6dd07f9ce502b06f0d4d5f47d055ab023aca97a83</originalsourceid><addsrcrecordid>eNo1UMtuwjAQdF9SKeUH2ot_IGH92sRHlLYUCYRUUK_Ijh1wlQcloRV_30jQOcxIM7tzGEKeGMSMgR7PVqssizkwFqtEomR4RR4YMp5KARyvyYCLBKMUAW_ISCfpfyb4LRkA0yJCJeCejNr2C3ogapWqAXETymL87ElO7bgd70NN86Zuj5U_0JePyYL-hm5HW18WkTvVpgo5_WnKzmx91OamDPWWdj7f1eH76Gn_LGVd0WyxXJ3tpmy2p0dyV5iy9aOLDsn67XWdvUfz5XSWTeZR0NBFHC0rLFidaPDInLCOC6MdOgdJoXOvgFvAApx0qpCJA6WMhf4mNzoxqRiS53Nt8N5v9odQmcNpc9lL_AGGn1kH</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Hyun-Woo Lee ; Ki-Han Kim ; Young-Kyoung Choi ; Ju-Hwan Shon ; Nak-Kyu Park ; Kwan-Weon Kim ; Chulwoo Kim ; Young-Jung Choi ; Byong-Tae Chung</creator><creatorcontrib>Hyun-Woo Lee ; Ki-Han Kim ; Young-Kyoung Choi ; Ju-Hwan Shon ; Nak-Kyu Park ; Kwan-Weon Kim ; Chulwoo Kim ; Young-Jung Choi ; Byong-Tae Chung</creatorcontrib><description>This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.</description><identifier>ISSN: 0193-6530</identifier><identifier>ISBN: 9781612843032</identifier><identifier>ISBN: 1612843034</identifier><identifier>EISSN: 2376-8606</identifier><identifier>EISBN: 1612843026</identifier><identifier>EISBN: 9781612843018</identifier><identifier>EISBN: 1612843018</identifier><identifier>EISBN: 9781612843025</identifier><identifier>DOI: 10.1109/ISSCC.2011.5746416</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Clocks ; CMOS technology ; Delay ; Random access memory ; Voltage control</subject><ispartof>2011 IEEE International Solid-State Circuits Conference, 2011, p.502-504</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5746416$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5746416$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hyun-Woo Lee</creatorcontrib><creatorcontrib>Ki-Han Kim</creatorcontrib><creatorcontrib>Young-Kyoung Choi</creatorcontrib><creatorcontrib>Ju-Hwan Shon</creatorcontrib><creatorcontrib>Nak-Kyu Park</creatorcontrib><creatorcontrib>Kwan-Weon Kim</creatorcontrib><creatorcontrib>Chulwoo Kim</creatorcontrib><creatorcontrib>Young-Jung Choi</creatorcontrib><creatorcontrib>Byong-Tae Chung</creatorcontrib><title>A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology</title><title>2011 IEEE International Solid-State Circuits Conference</title><addtitle>ISSCC</addtitle><description>This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.</description><subject>Bandwidth</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Delay</subject><subject>Random access memory</subject><subject>Voltage control</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>9781612843032</isbn><isbn>1612843034</isbn><isbn>1612843026</isbn><isbn>9781612843018</isbn><isbn>1612843018</isbn><isbn>9781612843025</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UMtuwjAQdF9SKeUH2ot_IGH92sRHlLYUCYRUUK_Ijh1wlQcloRV_30jQOcxIM7tzGEKeGMSMgR7PVqssizkwFqtEomR4RR4YMp5KARyvyYCLBKMUAW_ISCfpfyb4LRkA0yJCJeCejNr2C3ogapWqAXETymL87ElO7bgd70NN86Zuj5U_0JePyYL-hm5HW18WkTvVpgo5_WnKzmx91OamDPWWdj7f1eH76Gn_LGVd0WyxXJ3tpmy2p0dyV5iy9aOLDsn67XWdvUfz5XSWTeZR0NBFHC0rLFidaPDInLCOC6MdOgdJoXOvgFvAApx0qpCJA6WMhf4mNzoxqRiS53Nt8N5v9odQmcNpc9lL_AGGn1kH</recordid><startdate>201102</startdate><enddate>201102</enddate><creator>Hyun-Woo Lee</creator><creator>Ki-Han Kim</creator><creator>Young-Kyoung Choi</creator><creator>Ju-Hwan Shon</creator><creator>Nak-Kyu Park</creator><creator>Kwan-Weon Kim</creator><creator>Chulwoo Kim</creator><creator>Young-Jung Choi</creator><creator>Byong-Tae Chung</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201102</creationdate><title>A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology</title><author>Hyun-Woo Lee ; Ki-Han Kim ; Young-Kyoung Choi ; Ju-Hwan Shon ; Nak-Kyu Park ; Kwan-Weon Kim ; Chulwoo Kim ; Young-Jung Choi ; Byong-Tae Chung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-26b1fb0b9790e61d3bd23a9d6dd07f9ce502b06f0d4d5f47d055ab023aca97a83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Bandwidth</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Delay</topic><topic>Random access memory</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Hyun-Woo Lee</creatorcontrib><creatorcontrib>Ki-Han Kim</creatorcontrib><creatorcontrib>Young-Kyoung Choi</creatorcontrib><creatorcontrib>Ju-Hwan Shon</creatorcontrib><creatorcontrib>Nak-Kyu Park</creatorcontrib><creatorcontrib>Kwan-Weon Kim</creatorcontrib><creatorcontrib>Chulwoo Kim</creatorcontrib><creatorcontrib>Young-Jung Choi</creatorcontrib><creatorcontrib>Byong-Tae Chung</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hyun-Woo Lee</au><au>Ki-Han Kim</au><au>Young-Kyoung Choi</au><au>Ju-Hwan Shon</au><au>Nak-Kyu Park</au><au>Kwan-Weon Kim</au><au>Chulwoo Kim</au><au>Young-Jung Choi</au><au>Byong-Tae Chung</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology</atitle><btitle>2011 IEEE International Solid-State Circuits Conference</btitle><stitle>ISSCC</stitle><date>2011-02</date><risdate>2011</risdate><spage>502</spage><epage>504</epage><pages>502-504</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>9781612843032</isbn><isbn>1612843034</isbn><eisbn>1612843026</eisbn><eisbn>9781612843018</eisbn><eisbn>1612843018</eisbn><eisbn>9781612843025</eisbn><abstract>This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2011.5746416</doi><tpages>3</tpages></addata></record>
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subjects Bandwidth
Clocks
CMOS technology
Delay
Random access memory
Voltage control
title A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T10%3A36%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%201.6V%201.4Gb/s/pin%20consumer%20DRAM%20with%20self-dynamic%20voltage-scaling%20technique%20in%2044nm%20CMOS%20technology&rft.btitle=2011%20IEEE%20International%20Solid-State%20Circuits%20Conference&rft.au=Hyun-Woo%20Lee&rft.date=2011-02&rft.spage=502&rft.epage=504&rft.pages=502-504&rft.issn=0193-6530&rft.eissn=2376-8606&rft.isbn=9781612843032&rft.isbn_list=1612843034&rft_id=info:doi/10.1109/ISSCC.2011.5746416&rft_dat=%3Cieee_6IE%3E5746416%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1612843026&rft.eisbn_list=9781612843018&rft.eisbn_list=1612843018&rft.eisbn_list=9781612843025&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5746416&rfr_iscdi=true