A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life an...

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Hauptverfasser: Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Clocks
CMOS technology
Delay
Random access memory
Voltage control
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Beschreibung
Zusammenfassung:This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2011.5746416