Hierarchical yield estimation of large analog integrated circuits

Hierarchical yield estimation of large analog integrated circuits

A hierarchical methodology for parametric yield estimation is presented. The methodology employs a combination of behavioral and regression modeling. Three related techniques for hierarchical yield estimation are demonstrated on a large BiCMOS circuit combining discrete-time and continuous-time oper...

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Hauptverfasser: Kurker, C.M., Paulos, J.J., Gyurcsik, R.S., Jye-Chyi Lu
Format: Tagungsbericht
Sprache:eng
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Zusammenfassung:A hierarchical methodology for parametric yield estimation is presented. The methodology employs a combination of behavioral and regression modeling. Three related techniques for hierarchical yield estimation are demonstrated on a large BiCMOS circuit combining discrete-time and continuous-time operation.
DOI:10.1109/CICC.1992.589964