A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1989-10, Vol.24 (5), p.1198-1205
Hauptverfasser:	Lu, N.C.-C., Bronner, G.B., Kitamura, K., Scheuerlein, R.E., Henkels, W.H., Dhong, S.H., Katayama, Y., Kirihata, T., Niijima, H., Franch, R.L., Wang, W., Nishiwaki, M., Pesavento, F.L., Rajeevakumar, T.V., Sakaue, Y., Suzuki, Y., Iguchi, Y., Yano, E.
Format:	Artikel
Sprache:	eng
Schlagworte:	Aluminum Applied sciences Boron Circuits CMOS technology Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Laboratories MOS devices Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Testing Voltage Wiring
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