Gate Tunneling in Nanowire MOSFETs

In this letter, we report for the first time the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate (CG) nanowire (NW) transistor. An analytical 2-D gate tunneling model is developed and used to assess quantitatively the tunneling probability in the CG NW transistor. A reduction in gate tunneling probability is predicted in the CG NW transistor compared with a planar-gate (PG) transistor with the same dielectric thickness. This effect can be very significant when the dielectric curvature is large as in practical NW devices. A high- k gate dielectric is more effective in suppressing the gate tunneling in CG transistors than in PG transistors.