Processor-based decoupled PDP timing controller design
This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.
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| creator | Yeoul Na Seok Joong Hwang Cheol Ho Lee Junkyu Min Taejin Kim Seon Wook Kim |
| description | This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution. |
| doi_str_mv | 10.1109/ICCE.2011.5722909 |
| format | Conference Proceeding |
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| identifier | ISSN: 2158-3994 |
| ispartof | 2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, p.867-868 |
| issn | 2158-3994 2158-4001 |
| language | eng |
| recordid | cdi_ieee_primary_5722909 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Control systems Field programmable gate arrays Process control Prototypes Pulse width modulation Random access memory Timing |
| title | Processor-based decoupled PDP timing controller design |
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