Processor-based decoupled PDP timing controller design

Processor-based decoupled PDP timing controller design

This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Yeoul Na, Seok Joong Hwang, Cheol Ho Lee, Junkyu Min, Taejin Kim, Seon Wook Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Control systems
Field programmable gate arrays
Process control
Prototypes
Pulse width modulation
Random access memory
Timing
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.
ISSN:2158-3994
2158-4001
DOI:10.1109/ICCE.2011.5722909