A low-power management technique for high-performance domino circuits

Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68...

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Bibliographische Detailangaben
Hauptverfasser:	Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS integrated circuits Delay domino circuit Logic gates Power demand power management Semiconductor device measurement Voltage control
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Beschreibung
Zusammenfassung:	Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.
ISSN:	2153-6961 2153-697X
DOI:	10.1109/ASPDAC.2011.5722313