Resource constrained RTL partitioning for synthesis of multi-FPGA designs

In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the resources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail.