Issues in validating package compact thermal models for natural convection cooled electronic systems

A methodology is proposed for the validation of compact thermal models of electronic packages which utilizes data and simulations obtained from a simple but realistic system containing the package. The test system is the enclosure specified by the JEDEC Subcommittee, JC15.1 for thermal measurements...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Adams, V.H., Blackburn, D.L., Joshi, Y., Berning, D.W.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit simulation Computational fluid dynamics Computational modeling Electronic packaging thermal management Heat transfer Predictive models Semiconductor device packaging Surface resistance Temperature Thermal resistance
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