Improved implementation of a modified Discrete Cosine Transform on low-cost FPGA

In this paper, Discrete Cosine Transform hardware implementations are performed using two different modified Loeffler algorithms and are compared to the original one. The arithmetic modifications are presented and the correspondent algorithms are synthesized and implemented on a low-cost FPGA. The r...

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Bibliographische Detailangaben
Hauptverfasser:	Belkouch, S, El Aakif, M, Ouahman, A A, Hassani, M M
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Compression Discrete Cosine Transform Discrete cosine transforms Field programmable gate arrays Flow Graph Arithmetic Flow graphs FPGA OFDM Quantization
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Beschreibung
Zusammenfassung:	In this paper, Discrete Cosine Transform hardware implementations are performed using two different modified Loeffler algorithms and are compared to the original one. The arithmetic modifications are presented and the correspondent algorithms are synthesized and implemented on a low-cost FPGA. The results show a significant increase of the maximum frequency operation with a new proposed modified Loeffler algorithm.
DOI:	10.1109/ISVC.2010.5656248