Misleading energy and performance claims in sub/near threshold digital systems

Many of us in the field of ultra-low-V dd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower V dd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different V th definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's V dd and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need V dd to compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold V dd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-V dd systems. The outlined pitfalls also shed light on future directions in this field.