Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board
This paper presents the electrical characterization of annular TSV technology for full wafer applications. A possible utilization of this technology is the WaferBoard™, a reconfigurable circuit board for rapid system prototyping. Electrical resistance and capacitance of a single 2-4μm thick annular...
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creator | Diop, M D Radji, M Andre, W Blaquière, Yves Hamoui, A A Izquierdo, R |
description | This paper presents the electrical characterization of annular TSV technology for full wafer applications. A possible utilization of this technology is the WaferBoard™, a reconfigurable circuit board for rapid system prototyping. Electrical resistance and capacitance of a single 2-4μm thick annular TSV with a diameter of 110μm and a height of 350μm are measured to be about 10mΩ and 0.27pF, respectively. TSV yield of 98% is reached over the wafer. Results also show electrical failure of some TSVs due to poor via filling. |
doi_str_mv | 10.1109/EPEPS.2010.5642596 |
format | Conference Proceeding |
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A possible utilization of this technology is the WaferBoard™, a reconfigurable circuit board for rapid system prototyping. Electrical resistance and capacitance of a single 2-4μm thick annular TSV with a diameter of 110μm and a height of 350μm are measured to be about 10mΩ and 0.27pF, respectively. TSV yield of 98% is reached over the wafer. Results also show electrical failure of some TSVs due to poor via filling.</description><identifier>ISSN: 2165-4107</identifier><identifier>ISBN: 9781424468652</identifier><identifier>ISBN: 1424468655</identifier><identifier>EISBN: 1424468663</identifier><identifier>EISBN: 9781424468669</identifier><identifier>EISBN: 1424468671</identifier><identifier>EISBN: 9781424468676</identifier><identifier>DOI: 10.1109/EPEPS.2010.5642596</identifier><language>eng</language><publisher>IEEE</publisher><subject>annular TSV ; component ; Copper ; electrical resistance and capacitance ; Electrical resistance measurement ; Integrated circuit interconnections ; Resistance ; Routing ; Silicon ; Through-silicon vias ; WaferBoard</subject><ispartof>19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, 2010, p.245-248</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5642596$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5642596$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Diop, M D</creatorcontrib><creatorcontrib>Radji, M</creatorcontrib><creatorcontrib>Andre, W</creatorcontrib><creatorcontrib>Blaquière, Yves</creatorcontrib><creatorcontrib>Hamoui, A A</creatorcontrib><creatorcontrib>Izquierdo, R</creatorcontrib><title>Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board</title><title>19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems</title><addtitle>EPEPS</addtitle><description>This paper presents the electrical characterization of annular TSV technology for full wafer applications. A possible utilization of this technology is the WaferBoard™, a reconfigurable circuit board for rapid system prototyping. Electrical resistance and capacitance of a single 2-4μm thick annular TSV with a diameter of 110μm and a height of 350μm are measured to be about 10mΩ and 0.27pF, respectively. TSV yield of 98% is reached over the wafer. Results also show electrical failure of some TSVs due to poor via filling.</description><subject>annular TSV</subject><subject>component</subject><subject>Copper</subject><subject>electrical resistance and capacitance</subject><subject>Electrical resistance measurement</subject><subject>Integrated circuit interconnections</subject><subject>Resistance</subject><subject>Routing</subject><subject>Silicon</subject><subject>Through-silicon vias</subject><subject>WaferBoard</subject><issn>2165-4107</issn><isbn>9781424468652</isbn><isbn>1424468655</isbn><isbn>1424468663</isbn><isbn>9781424468669</isbn><isbn>1424468671</isbn><isbn>9781424468676</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kM9Kw0AYxFdUsNa8gF72BVL3f7JHKbEKBQv2Xr7d7DZfiY1sEsU-vQHrXIbfDMxhCLnnbME5s4_Vptq8LwSbWBsltDUX5JYroZQpjZGXJLNF-c9aXJGZ4EbnirPihmR9f2CTtCikFDNyqNrgh4QeWuobSOCHkPAEA3ZH2kUKx-PYQqJDk7px39AeW_RT9YXQ09glCjSFKYi4HxO4NtBviCHlPZ5CTT0mP-JAXQepviPXEdo-ZGefk-1ztV2-5Ou31evyaZ2jZUPuo9LClNoVTJjaMqeldZELF5x3XLHCBi-44KVyvHayiFqV0qlScw1eW5Bz8vA3iyGE3WfCD0g_u_NT8hd9e1xf</recordid><startdate>201010</startdate><enddate>201010</enddate><creator>Diop, M D</creator><creator>Radji, M</creator><creator>Andre, W</creator><creator>Blaquière, Yves</creator><creator>Hamoui, A A</creator><creator>Izquierdo, R</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201010</creationdate><title>Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board</title><author>Diop, M D ; Radji, M ; Andre, W ; Blaquière, Yves ; Hamoui, A A ; Izquierdo, R</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-cf452685b7026d90b539bf12bebcb14079ec212184b1db37f5483b48515ac59a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>annular TSV</topic><topic>component</topic><topic>Copper</topic><topic>electrical resistance and capacitance</topic><topic>Electrical resistance measurement</topic><topic>Integrated circuit interconnections</topic><topic>Resistance</topic><topic>Routing</topic><topic>Silicon</topic><topic>Through-silicon vias</topic><topic>WaferBoard</topic><toplevel>online_resources</toplevel><creatorcontrib>Diop, M D</creatorcontrib><creatorcontrib>Radji, M</creatorcontrib><creatorcontrib>Andre, W</creatorcontrib><creatorcontrib>Blaquière, Yves</creatorcontrib><creatorcontrib>Hamoui, A A</creatorcontrib><creatorcontrib>Izquierdo, R</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Diop, M D</au><au>Radji, M</au><au>Andre, W</au><au>Blaquière, Yves</au><au>Hamoui, A A</au><au>Izquierdo, R</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board</atitle><btitle>19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems</btitle><stitle>EPEPS</stitle><date>2010-10</date><risdate>2010</risdate><spage>245</spage><epage>248</epage><pages>245-248</pages><issn>2165-4107</issn><isbn>9781424468652</isbn><isbn>1424468655</isbn><eisbn>1424468663</eisbn><eisbn>9781424468669</eisbn><eisbn>1424468671</eisbn><eisbn>9781424468676</eisbn><abstract>This paper presents the electrical characterization of annular TSV technology for full wafer applications. A possible utilization of this technology is the WaferBoard™, a reconfigurable circuit board for rapid system prototyping. Electrical resistance and capacitance of a single 2-4μm thick annular TSV with a diameter of 110μm and a height of 350μm are measured to be about 10mΩ and 0.27pF, respectively. TSV yield of 98% is reached over the wafer. Results also show electrical failure of some TSVs due to poor via filling.</abstract><pub>IEEE</pub><doi>10.1109/EPEPS.2010.5642596</doi><tpages>4</tpages></addata></record> |
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issn | 2165-4107 |
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subjects | annular TSV component Copper electrical resistance and capacitance Electrical resistance measurement Integrated circuit interconnections Resistance Routing Silicon Through-silicon vias WaferBoard |
title | Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board |
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