A 0.9mW PLL integrated in an ultra-low-power SoC for WPAN and WBAN applications

In this paper we present a low-power frequency synthesizer fabricated as a part of the ultra low-power wireless transceiver system named TELRAN™. The synthesizer consists of an integer-N Phase Locked Loop (PLL), operating in the frequency range 766-850MHz, with automatic tank selection hardware state machine. The System on Chip (SoC) has been fabricated in a 0.13μm CMOS technology. The PLL occupies an area of 0.98mm 2 , dissipating 0.87mA from a 1V supply. The measured phase noise at 10kHz and 100kHz from the carrier is better than -60dBc and -93dBc, respectively.