A configurable cascaded continuous-time ΔΣ modulator with up to 15MHz bandwidth
A reconfigurable cascaded continuous-time 3-1 ΔΣ modulator with low PVT sensitivity was developed and implemented in 65nm digital CMOS. The 0.17mm 2 chip achieves 67/55dB SNR and 70/61dB DR at 10/15MHz bandwidth with only 208MHz clock frequency and 10.5mW power consumption from a 1.3V supply.
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Format: | Tagungsbericht |
Sprache: | eng |
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Zusammenfassung: | A reconfigurable cascaded continuous-time 3-1 ΔΣ modulator with low PVT sensitivity was developed and implemented in 65nm digital CMOS. The 0.17mm 2 chip achieves 67/55dB SNR and 70/61dB DR at 10/15MHz bandwidth with only 208MHz clock frequency and 10.5mW power consumption from a 1.3V supply. |
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ISSN: | 1930-8833 2643-1319 |
DOI: | 10.1109/ESSCIRC.2010.5619734 |