A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns
A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V DD = 1.0V and nominal proc...
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creator | Jacunski, M Anand, D Busch, R Fifield, J Lanahan, M Lane, P Paparelli, A Pomichter, G Pontius, D Roberge, M Sliva, S |
description | A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V DD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock. |
doi_str_mv | 10.1109/CICC.2010.5617634 |
format | Conference Proceeding |
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subjects | Arrays Capacitance Capacitors Clocks Random access memory Timing |
title | A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns |
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