An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection

An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection

An 8-bit, 1.5GS/s flash ADC is presented. Comparators are digitally calibrated using statistical selection. INL of 1.32 LSB and DNL of 1.23 LSB are achieved. Average comparator noise of 5mV rms (1.3 LSB) limits SNDR to 37dB at low frequencies. Total power is 35mW, 20mW in the S&H and 15mW in the...

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Bibliographische Detailangaben
Hauptverfasser: Proesel, J, Keskin, G, Plouchart, Jean-Olivier, Pileggi, Lawrence
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Calibration
Clocks
CMOS integrated circuits
Noise
Redundancy
Transistors
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Beschreibung
Zusammenfassung:An 8-bit, 1.5GS/s flash ADC is presented. Comparators are digitally calibrated using statistical selection. INL of 1.32 LSB and DNL of 1.23 LSB are achieved. Average comparator noise of 5mV rms (1.3 LSB) limits SNDR to 37dB at low frequencies. Total power is 35mW, 20mW in the S&H and 15mW in the ADC core. The figure of merit is 0.42pJ/conv, the best reported for 1+GS/s, 7+-bit ADCs.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2010.5617410