A Discrete-Time Input \Delta\Sigma ADC Architecture Using a Dual-VCO-Based Integrator

This brief presents a hybrid analog-digital ΔΣ analog-to-digital converter architecture with a pseudodifferential integrator based on current-controlled oscillators (CCOs). Two oscillators driven by differential input signals and followed by digital counters are used to form a quantizer whose output is digitally integrated. This pseudodifferential circuit configuration reduces the relative quantization step size and also improves linearity by canceling even-order distortion. Instead of driving a CCO with a continuous-time current input or a V - I converter, a double-sampled switched-capacitor circuit is used to dump charge packets proportional to the signal voltage into the input of each oscillator. A hybrid analog-digital modulator allows for further signal processing in the digital domain to produce a low-resolution output suitable for a feedback digital-to-analog converter and an all-digital excess-loop-delay compensation feedback path. Simulation results show a signal-to-noise-plus-distortion ratio of 83.9 dB in a 2-MHz bandwidth.